(a) Field of the Invention
The present invention relates to a wiring board and a manufacturing method of the same. More particularly, the present invention relates to a wiring board including a pad (a portion of a wiring layer) for use in mounting an electronic component such as a semiconductor element (chip) or in bonding an external connection terminal thereto, and to a manufacturing method of the same.
The wiring board is hereinafter also referred to as a “semiconductor package” for the sake of convenience, in the meaning that the wiring board has the role as a package for mounting a semiconductor element (chip) or the like thereon.
(b) Description of the Related Art
In a wiring board, a pad is defined at a predetermined position in a wiring layer, which is, the outermost layer. To this pad, an external connection terminal (such as a solder ball or a pin) for use in mounting the wiring board on a motherboard or the like, or an electrode terminal or the like of a semiconductor element to be mounted on the wiring board is connected. Then, the wiring layer except this pad portion is covered by an insulating layer (typically, a resin layer). Specifically, a corresponding portion of the outermost insulating layer is opened, and the pad is exposed through this opening portion. This pad is formed so that the surface thereof can be flush with the surface of the insulating layer (resin layer), or the surface thereof can be formed at a position recessed from the surface of the insulating layer (resin layer) toward an inner side of the board.
In general, the pad has a layer structure in which multiple metal layers are stacked one on top of another. As the typical layer structure, there is a two-layer structure formed of a gold (Au) layer and a nickel (Ni) layer. The Au layer of this pad is exposed from the insulating layer (resin layer), and a via (which is a conductor filled into a via hole formed on the resin layer in the board and mutually connects the wiring layers) is connected to the Ni layer on this Au layer. This Ni layer is provided for preventing a metal contained in the via (typically, copper (Cu)) from diffusing into the Au layer.
However, since the Ni layer is readily oxidized, there occurs an inconvenience when a wiring board including the aforementioned two-layer (Au/Ni) structure pad, particularly, a wiring board of a type called “coreless board,” is fabricated. The basic process of this coreless board includes: preparing a temporary substrate as a support member; then forming a pad on this temporary substrate; then, sequentially forming a required number of build-up layers (resin layers including via holes, wiring layers including inner portions of the via holes); and thereafter, removing the temporary substrate, finally. Specifically, the via is formed and then connected to the Ni layer of the pad after the pad is formed. For this reason, Ni oxide is formed on the surface of the Ni layer after the formation of the pad. As a result, when the via is connected to the Ni layer including the oxide formed thereon, an adhesion between the pad and the via decreases due to influence of the oxide, and electrical connection reliability between the pad and the via is damaged.
The applicant of this application has proposed a technique of coping with the inconvenience. An example of the technique is described in Japanese unexamined Patent Publication (JPP) (Kokai) 2008-141070. In the technique disclosed in this publication, in a wiring board including pads and vias connected to the pads, multiple metal layers stacked one on top of another and forming the pads include: a metal layer (Au layer) exposed from the wiring board; and a metal layer (Ni layer) provided on this metal (Au) layer and preventing a metal contained in the vias from diffusing into the metal (Au) layer. In addition, the multiple metal layers further includes a metal layer (Cu layer) provided between this metal (Ni) layer and the vias, the metal layer (Cu layer) being harder to be oxidized than the metal (Ni) layer. Specifically, a possibility that oxide is interposed between the pads and the vias is practically eliminated by interposing the Cu layer, which is hard to be oxidized, between the vias and the Ni layer. Thereby, the adhesion between the pads and the vias is improved.
Although the technique (the aforementioned publication) for solving the inconvenience observed in the conventional pad having the two-layer (Au/Ni) structure has been proposed as described above, in this technique, nothing is mentioned as to the thickness of each of the metal layers forming the pad and a tensile strength of the pad in particular.
Meanwhile, along with a demand for making a wiring board thinner, a wiring layer and an insulating layer (resin layer) tend to be formed as thin as possible, so that the thickness of the pad to be defined at a portion of the outermost wiring layer needs to be thin as well in accordance with the wring layer. This means that the thickness of each of the metal layers forming the pads described in the aforementioned publication, namely, the thickness of the metal layer (Cu layer) contributing to the improvement in the adhesion with the via becomes thinner as well.
When the thickness of the Cu layer of the pads becomes thin as described above, the surface area of the wall surface of each of the pads, which is in contact with a resin layer (insulating layer) therearound, becomes small, and the adhesion with the resin layer decreases. As a result, a tensile strength when external connection terminals (such as solder balls or pins) or electrode terminals or the like of a semiconductor element are bonded to these pads decreases. Then, a problem that the pads are peeled off depending on circumstances possibly arises. This problem leads to deterioration in performance of the wiring board, and consequently, leads to a decrease in reliability in mounting a semiconductor element or the like on the wiring board or in mounting the wiring board on a motherboard or the like.
The problem of this kind is not necessarily unique to the coreless board, and possibly occurs in the same manner on a wiring board of a type having a core board. Specifically, the aforementioned problem possibly occurs in the same manner on any wiring board which includes a pad formed of multiple metal layers stacked one on top of another as described above and having a structure in which the metal layer (Cu layer) on a side connected to the via is formed with a thin thickness.